1. Field of the Invention
The present invention relates to an interconnect layout method.
2. Related Art
Recently, following high integration and reduction in size of semiconductor devices, fluctuations in shape of gate patterns during forming the gate patterns has greatly influenced on fluctuations in electric characteristics such as an ON current and a threshold voltage. It is, therefore, required to provide a technique for controlling fluctuations in shape of the gate patterns so as to improve semiconductor device yield by improving the electric characteristics.
As shown in FIG. 4, in a conventional gate layout as disclosed in Japanese Laid-open patent publication No. 1997-311432 (No. H09-311432), a so-called vacant area 9 is present between actual patterns 8a to 8d and actual patterns 8e to 8h employed for interconnects. Due to this, the shape of the actual patterns arranged closer to the vacant area 9 are disadvantageously made thinner.
To solve this disadvantage and control the fluctuations in shape of the gate patterns, a technique for controlling fluctuations in gate length while making optical diffraction and microloading effects constant is disclosed in Japanese Laid-open patent publication No. 2000-112114.
FIG. 5 shows one example of a gate layout method using the technique disclosed in Japanese Laid-open patent publication No. 2000-112114.
In a gate layout 10 shown in FIG. 5, a dummy gate pattern 3 and a dummy gate pattern 4 which is equal in device structure to actual gates but which include no circuitry functions are provided to be separated from a gate pattern 1 and a gate pattern 2. Because of this, a smallest distance p between each gate pattern and each dummy gate pattern is substantially constant except for gate terminal portions and corner portions.
A gate length of each gate pattern is equal to or smaller than 0.5λ/NA, center-to-center distances p between two adjacent patterns of the gate pattern 1 and the gate pattern 2 and the dummy gate pattern 3 and the dummy gate pattern 4 are equal to or smaller than 2λ/NA, and a fluctuation width of the center-to-center distance p is within a range between −10% and +10% of the distance p.